At various stages during the manufacture of an integrated circuit on a semiconductor substrate it may be necessary to create an area of oxide coating. Traditionally, semiconductor substrates are silicon and the desired oxide coating is silicon dioxide. Oxidation of silicon is a thermally dependant process, generally performed at temperatures of between 900-1050.degree. C. It is known that the thermal oxidation rate of silicon at those temperatures is further dependent on many parameters, including, but not limited to: the crystallographic orientation of the Si; the Si doping level; the presence of halogen impurities (Cl, HCl, TCA, TCE) in the gas phase; the pressure during growth; the presence of a plasma during growth; and the presence of a photon flux during growth. In addition to the use of halogens in the gas phase during an oxidation step, it is also known to use ion implantation to selectively implant halogen ions in silicon to provide simultaneous differential (greater) oxidation of the implanted regions vs. non-implanted regions during an oxidation step.
The high temperatures traditionally used for silicon oxidation have drawbacks, however, at certain stages of semiconductor manufacture. For instance, high temperatures may cause undesired diffusion of dopants, which in turn may degrade performance of the semiconductor device. Thus, for any oxidation step performed after well dopants are in place, or after source and drain diffusion regions have been created, the oxidation step creates the undesired effect of redistributing dopants by diffusion.
For example, after pattern etching, such as reactive ion etching (RIE) of a polygate, certain features in the device structure require an oxidation step to repair undesired etch features or defects. These defects often occur on sidewalls or non-planar structures of the device.
Referring now to FIGS. 1-4, there is illustrated a process for etching a gate structure 20. As shown in FIG. 1, a typical semiconductor wafer 9 may comprise a doped well 10 in substrate 11, a gate dielectric or oxide layer 12 above the well, and a polysilicon layer 14 disposed on top of the gate oxide layer. The typical process for making a patterned gate structure 20 (shown in FIG. 4) comprises applying a photoresist 18 over the polysilicon layer 14 as shown in FIG. 1. The photoresist 18 is then exposed and developed in a pattern that exposes regions 22, as shown in FIG. 2. The layers under the exposed regions 22 will be removed in an etching process such as RIE, while the layers under protective photoresist 18' will not be removed.
RIE removes the exposed regions 22 in an essentially anisotropic, or vertical, manner to create isolated gate structure 20 under protective photoresist 18', as shown in FIG. 3. Often, to fully remove all the unwanted polysilicon gate material from topographic features in the device structures, a timed or end-pointed "over-etch" is used. During this over-etch, the thin gate oxide layer 12 under the gate polysilicon layer 14 may be etched out from under the edge 15 of the gate polysilicon layer, causing undercut 24 in sidewall 26. The sidewall 26 is critical for device reliability (electric fields, and therefore oxide damage, are most severe here), so the gate oxide 12 must be re-grown on sidewall 26 before any further processing is done. Typically, the photoresist 18 is removed, and a sidewall oxidation process oxidizes the polysilicon gate edge 15 and the adjacent area. The sidewall oxidation fills in undercut 24 in gate oxide 12 of FIG. 3, generally resulting in a repaired gate oxide 112, as shown in FIG. 4. Gate oxide 112 as shown in FIG. 4 after sidewall oxidation, is generally thicker than the original gate oxide 12 of FIG. 3. Excess portions of the repaired gate oxide 12 beyond the portion directly under gate polysilicon layer 14, may later be removed.
A high-temperature oxidation (900-1050.degree. C.) is conventionally used for this sidewall oxidation. Because the high-temperature oxidation is done after all the doping is completed in well 10, the high-temperatures may diffuse the dopants, potentially resulting in degraded device performance.
In view of the shortcomings of the prior art, there is a need for a silicon oxidation process that minimizes dopant diffusion.